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ADMV7310BCEZ データシート(PDF) 2 Page - Analog Devices |
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ADMV7310BCEZ データシート(HTML) 2 Page - Analog Devices |
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2 / 29 page ![]() ADMV7310 Data Sheet Rev. A | Page 2 of 29 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Interface Schematics..................................................................... 8 Typical Performance Characteristics ............................................. 9 Detector Performance................................................................ 19 Return Loss Performance.......................................................... 21 Spurious Performance................................................................ 22 Theory of Operation ...................................................................... 23 Mixer and LO Path..................................................................... 23 Envelope Detector, VGA, and Power Detector ...................... 23 Power Amplifier and Power Detector ..................................... 23 Applications Information .............................................................. 25 Power-Up Bias Sequence........................................................... 25 Power-Down Bias Sequence ..................................................... 25 LO Nulling................................................................................... 25 Gain Tuning Procedure ............................................................. 26 Layout .......................................................................................... 27 Typical Application Circuit........................................................... 28 Outline Dimensions....................................................................... 29 Ordering Guide .......................................................................... 29 REVISION HISTORY 10/2019—Revision A: Initial Version |
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