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ADRF6755ACPZ データシート(PDF) 19 Page - Analog Devices

部品番号 ADRF6755ACPZ
部品情報  100 MHz to 2400 MHz I/Q Modulator with Integrated Fractional-N PLL and VCO
PDF  48 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADRF6755ACPZ データシート(HTML) 19 Page - Analog Devices

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Data Sheet
ADRF6755
Rev. B | Page 19 of 48
Figure 41. Attenuator Absolute Step Accuracy Distribution at Nominal
and Worst-Case Conditions, LO > 300 MHz, All Attenuation Steps
Figure 42. Gain Flatness in any 40 MHz for all Attenuation Steps vs.
LO Frequency at Nominal Conditions
Figure 43. Attenuator Setting Time to 0.2 dB for Small Steps (1 dB to 6 dB) at
Nominal Conditions
Figure 44. Attenuator Settling Time to 0.5 dB for Small Steps
(1 dB to 6 dB) at Nominal Conditions
Figure 45. Attenuator Settling Time to 0.2 dB for Large Steps
(7 dB to 47 dB) at Nominal Conditions
Figure 46. Attenuator Settling Time to 0.5 dB for Large Steps
(7 dB to 47 dB) at Nominal Conditions
0
5
10
15
20
25
30
–5.0 –4.6 –4.2 –3.8 –3.4 –3.0 –2.6 –2.2 –1.8 –1.4 –1.0 –0.6 –0.2 0.2
ATTENUATOR ABSOLUTE STEP ACCURACY (dB)
NOMINAL
WORST CASE
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
100 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
LO FREQUENCY (MHz)
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STARTING ATTENUATOR STEP
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STARTING ATTENUATOR STEP
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STARTING ATTENUATOR STEP



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