ACE24LA128A

Two-wire Serial EEPROM

VER 1.1

6

Figure 3: Output Acknowledge

Device Addressing

The 128K EEPROM devices all require an 8-bit device address word following a start condition to enable

the chip for a read or write operation (see Figure 4)

MSB

LSB

1

0

1

0

A2

A1

A0

R/W

Figure 4: Device Address

The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits

as shown. This is common to all the Serial EEPROM devices.

The 128K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the

same bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2, A1 and

A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed

to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip

will return to a standby state.

DATA SECURITY:

The ACE24LA128A has a hardware data protection scheme that allows the user to write protect the entire

memory when the WP pin is at VCC.

Write Operations

Byte Write:

A write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock

in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the

addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At

disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure

5).