9.2.2 Detailed Design Procedure

The following items must be determined before starting design of a CDCDB800 socket:

• Output Enable Control Method

9.2.2.1 Output Enable Control Method

The device provides an option to either use SMBus programmed registers (software) to control the outputs or by

using the hardware OE# pins. In case of using software to control the outputs, the hardware OE# pins can be left

floating as each of these pins have a pull-down to ground. Please refer Table 8-1 and Register Maps for more

information on programming the register.

When the user wants to control the outputs with the hardware OE# pins, they can do so for example by

connecting these pins to a GPIO controller and follow the Table 5-1 to set the outputs to HIGH/LOW. The bits

OUT_EN_CLK7 to OUT_EN_CLK0 used to control the outputs are shown in registers OECR1 (OECR1 Register

Field Descriptions) and OECR2 (OECR2 Register Field Descriptions). These register bits are set to 1 by default

to ensure that the outputs are "software enabled" and their state is therefore set by hardware OE# pins.

9.2.3 Application Curves

Figure 6-1 in the Typical Characteristics section can be used as both an application curve and a typical

characteristics plot in this example.

The Output Slew Rate vs. CAPTRIM Code and Slew Rate Variation Across Temperature for Different CAPTRIM

Code show characterization data for the Output slew rate for various CAPTRIM codes and across temperature.

Customers can use these plots as reference for choosing the appropriate output slew rate based on their system

requirement.

.

Figure 9-2. Output Slew Rate vs. CAPTRIM Code

Temperature (qC)

120

100

80

60

40

20

0

-20

-40

-60

0

1

2

3

4

5

6

7

D002

0 - 3.3 V

1 - 3.3 V

2 - 3.3 V

3 - 3.3 V

4 - 3.3 V

5 - 3.3 V

6 - 3.3 V

7 - 3.3 V

8 - 3.3 V

9 - 3.3 V

10 - 3.3 V

11 - 3.3 V

12 - 3.3 V

13 - 3.3 V

.

Figure 9-3. Slew Rate Variation Across

Temperature for Different CAPTRIM Code

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CDCDB800

SNAS818 – JULY 2021

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