PLL102-05

Low Skew Output Buffer

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/22/05 Page 3

3. Switching Characteristics

PARAMETERS

SYMBOL

DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Output Frequency

t1

25

60

MHz

Duty Cycle ( t2

÷ t1 )

Dt1

Measured at 1.4V,

40.0

50.0

60.0

%

Duty Cycle ( t2

÷ t1 )

Dt2

Measured at 1.4V

45.0

50.0

55.0

%

Rise Time

Measured between 0.8V

1.2

1.5

ns

Fall Time

Measured between 2.0V

1.2

1.5

ns

Output to Output Skew

All outputs equally loaded,

250

ps

Delay, REF Rising Edge to

CLKOUT Rising Edge

Measured at 1.4V

0

±350

ps

Device to Device Skew

CLKOUT pins of devices

0

700

ps

Cycle to Cycle Jitter

Loaded outputs

150

ps

PLL Lock Time

Stable power supply, valid

clock presented on REF pin

1.0

ms

Jitter; Absolute Jitter

70

100

ps

Jitter; 1-sima

10

20

ps

SWITCHING WAVEFORMS

Duty Cycle Timing

t1

t2

1.4V

1.4V

1.4V

Output - Output Skew

1.4V

1.4V

T

SKEW

Output

Output