Preliminary

PLL602-10

96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 11/06/02 Page 1

FEATURES

• Low phase noise output for the 96MHz to

400MHz range (-134 dBc at 10kHz offset).

• Selectable CMOS, PECL and LVDS output.

• 12 to 25MHz crystal input.

• Output Enable selector.

• 3.3V operation.

• Available in DIE (65 mil x 62 mil).

DESCRIPTIONS

The PLL602-10 is a monolithic low jitter and low

phase noise (-134dBc/Hz @ 10kHz offset) XO IC

Die, with CMOS, LVDS and PECL output, for 96MHz

to 400MHz output range, using a low frequency

crystal.

The same die can be used as a XO with output

to selector pads allowing bonding options (see

Divider Selection Table on this page). This makes

the PLL602-10 ideal for a wide range of applications.

DIE SPECIFICATIONS

Name

Value

Size

62 x 65 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

10 mil

DIE CONFIGURATION

MULTIPLIER SELECTION

Pad #19

MULTIPLIER

OUTPUT RANGE

0

192 – 400 MHz

1

96 – 200 MHz

Note:

Selector pad defaults to ‘1’, wire bond to GND to set to ‘0’

OUTPUT SELECTION AND ENABLE

Pad #18

OUTSEL1

Pad #25

OUTSEL0

Selected Output

0

0

High Drive CMOS

0

1

Standard CMOS

1

0

PECL

1

1

LVDS

OE (Pad #30)

State

0

Tri-state

1 (Default)

Output enabled

BLOCK DIAGRAM

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

VCO

Divider

XTAL

OSC

CLKBAR

OE

XIN

XOUT

CLK

SELECT

18

19

20

21

23

25

7

13

10

26

29

31

Y

X

(0,0)

(1550,1475)

65 mil

24

22

17

16

15

14

12

11

9

8

6

1

2

3

4

5

27

28

30