AT25QL321 datasheet(18/79 Pages) DIALOG

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AT25QL321

DS-25QL321–131C–5/2017

7.4

Write Disable (04h)

The Write Disable instruction is to reset the Write Enable Latch (WEL) bit in the Status Register. To enter the Write Disable

instruction, CS goes low prior to the instruction “04h” into Data Input (SI) pin on the rising edge of SCK, and then driving CS

high. WEL bit is automatically reset write- disable status of “0” after Power‐up and upon completion of the every Program,

Erase and Write Status Register instructions.

Figure 7-3. Write Disable Instruction for SPI Mode (left) and QPI Mode (right)

7.5

Read Status Register-1 (05h) and Read Status Register-2 (35h)

The Read Status Register instructions are to read the Status Register. The Read Status Register can be read at any

time (even in program/erase/write Status Register and Write Security Register condition). It is recommended to check

the BUSY bit before sending a new instruction when a Program, Erase, Write Status Register or Write Status Register

operation is in progress.

The instruction is entered by driving CS low and sending the instruction code “05h” for Status Register-1 or “35h” for Status

Register-2 into the SI pin on the rising edge of SCK. The status register bits are then shifted out on the SO pin at the falling

edge of SCK with most significant bit (MSB) first as shown in (Figure 7-4 and Figure 7-5). The Status Register can be read

continuously. The instruction is completed by driving CS high.

Figure 7-4. Read Status Register Instruction (SPI Mode)

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