Preliminary

PLL502-21

384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 08/10/01 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

VDD

1,2,16

P

+3.3V Power supply connectors.

XIN

3

I

Crystal input pin.

XOUT

4

I

Crystal output pin.

OE

5

I

Output enable input pin. Disables (tri-state) output when low. Internal

pull-up enables output by default if pin is not connected to low.

VIN

6

I

Frequency control voltage input pin.

GND

7,8,9,10

P

GND Power connectors.

GND_BUF

11,15

P

GND connector for output buffers.

CLK

12

O

True clock output pin.

VDD_BUF

13

P

+3.3V Power supply connector for output buffers.

CLKB

14

O

Complementary clock output pin.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

7

V

Input Voltage, dc

V

Output Voltage, dc

V

Storage Temperature

-65

150

°C

Ambient Operating Temperature

0

70

°C

Junction Temperature

125

°C

Lead Temperature (soldering, 10s)

260

°C

Input Static Discharge Voltage Protection

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other

conditions above the operational limits noted in this specification is not implied.