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AFE7950 データシート(PDF) 2 Page - Texas Instruments |
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AFE7950 データシート(HTML) 2 Page - Texas Instruments |
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2 / 9 page ![]() 4 Description (continued) Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog- to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200 MHz for four RX without FB paths or 600 MHz with two FB paths (1200 MHz BW each). AFE7950 SBASA41A – FEBRUARY 2021 – REVISED SEPTEMBER 2021 www.ti.com 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AFE7950 |
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