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authentication, IP protection

SUBSYSTEM BOARD 5822

Alcatraz (MAXREFDES34#): SHA-256 Secure

Authentication Design

By:

Michael

D'Onofrio

Feb 12, 2014

Abstract: The Alcatraz (MAXREFDES34#) subsystem provides a reference design for securing Xilinx

FPGAs to protect IP and prevent attached peripheral counterfeiting. The system implements a SHA-256

challenge-response between the FPGA and a DS28E15 secure authenticator. Boards for purchase,

hardware, and firmware design files provide complete system information for rapid prototyping and

development.

Introduction

Smart factories, industrial and

medical applications employ the

flexibility and high performance of

modern FPGAs. As these systems

become increasingly connected,

security emerges as a paramount

feature to protect IP, enable

system features using software

and prevent counterfeiting. The

Alcatraz (MAXREFDES34#)

subsystem reference design uses

the DS28E15 to immediately

defines a combined SHA-256 processor and 1-Wire Master on the host FPGA.

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