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DS31256 データシート(PDF) 73 Page - Maxim Integrated Products

部品番号 DS31256
部品情報  256-Channel, High-Throughput HDLC Controller
PDF  183 Pages
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メーカー  MAXIM [Maxim Integrated Products]
ホームページ  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS31256 データシート(HTML) 73 Page - Maxim Integrated Products

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DS31256 256-Channel, High-Throughput HDLC Controller
73 of 183
Bits 8 to 11/Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These four bits determine how
many flags and interfill bytes are sent between consecutive packets.
TFG3
TFG2
TFG1
TFG0
ACTION
0
0
0
0
Share closing and opening flag
0
0
0
1
Closing flag/no interfill bytes/opening flag
0
0
1
0
Closing flag/1 interfill byte/opening flag
0
0
1
1
Closing flag/2 interfill bytes/opening flag
0
1
0
0
Closing flag/3 interfill bytes/opening flag
0
1
0
1
Closing flag/4 interfill bytes/opening flag
0
1
1
0
Closing flag/5 interfill bytes/opening flag
0
1
1
1
Closing flag/6 interfill bytes/opening flag
1
0
0
0
Closing flag/7 interfill bytes/opening flag
1
0
0
1
Closing flag/8 interfill bytes/opening flag
1
0
1
0
Closing flag/9 interfill bytes/opening flag
1
0
1
1
Closing flag/10 interfill bytes/opening flag
1
1
0
0
Closing flag/11 interfill bytes/opening flag
1
1
0
1
Closing flag/12 interfill bytes/opening flag
1
1
1
0
Closing flag/13 interfill bytes/opening flag
1
1
1
1
Closing flag/14 interfill bytes/opening flag
Bit 12/Transmit Zero Stuffing Disable (TZSD). When this bit is set low, the HDLC engine performs zero
stuffing on the outgoing data stream. When this bit is set high, the outgoing data stream is not zero stuffed. This
bit is ignored when the HDLC engine is configured in the transparent mode (TTRANS = 1).



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