EDB8164B4PR-1DATF-R datasheet(119/152 Pages) MICRON

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Table 80: Differential Output Slew Rate Definition

Description

Measured

Defined by

From

Differential output slew rate for rising edge

VOL,diff(AC)

VOH,diff(AC)

[VOH,diff(AC) - VOL,diff(AC)ΔTRdiff

Differential output slew rate for falling edge

VOH,diff(AC)

VOL,diff(AC)

[VOH,diff(AC) - VOL,diff(AC)ΔTFdiff

Note:

1. Output slew rate is verified by design and characterization and may not be subject to

production testing.

Figure 77: Differential Output Slew Rate Definition

OH,diff(AC)

OL,diff(AC)

Time

∆TF

diff

∆TR

diff

Table 81: Differential Output Slew Rate

Parameter

Symbol

Value

Unit

Min

Max

Differential output slew rate (output impedance = 40

Ω 

SRQdiff

3.0

7.0

V/ns

Differential output slew rate (output impedance = 60

Ω 

SRQdiff

2.0

5.0

V/ns

Notes:

1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = single-

ended signals.

2. Measured with output reference load.

3. The output slew rate for falling and rising edges is defined and measured between

VOL(AC) and VOH(AC).

4. Slew rates are measured under typical simultaneous switching output (SSO) conditions,

with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per

data byte driving LOW.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Output Characteristics and Operating Conditions

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

119

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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