PDU18F datasheet(2/5 Pages) DATADELAY

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PDU18F

APPLICATION NOTES

ADDRESS UPDATE

The PDU18F is a memory device. As such,

special precautions must be taken when

changing the delay address in order to prevent

spurious output signals. The timing restrictions

are shown in Figure 1.

After the last signal edge to be delayed has

appeared on the OUT pin, a minimum time, TOAX,

is required before the address lines can change.

This time is given by the following relation:

TOAX = max { (Ai - A i-1) * TINC , 0 }

where A i-1 and Ai are the old and new address

codes, respectively. Violation of this constraint

may, depending on the history of the input signal,

cause spurious signals to appear on the OUT

pin. The possibility of spurious signals persists

until the required TOAX has elapsed.

A similar situation occurs when using the EN/

signal to disable the output while IN is active. In

this case, the unit must be held in the disabled

state until the device is able to “clear” itself. This

is achieved by holding the EN/ signal high and

the IN signal low for a time given by:

TDISH = Ai * TINC

Violation of this constraint may, depending on the

history of the input signal, cause spurious signals

to appear on the OUT pin. The possibility of

spurious signals persists until the required TDISH

has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input

pulse width and period listed in the AC

Characteristics table. The recommended

conditions are those for which the delay

tolerance specifications and monotonicity are

guaranteed. The suggested conditions are

those for which signals will propagate through the

unit without significant distortion. The absolute

conditions are those for which the unit will

produce some type of output for a given input.

When operating the unit between the

recommended and absolute conditions, the

delays may deviate from their values at low

frequency. However, these deviations will

remain constant from pulse to pulse if the input

pulse width and period remain fixed. In other

words, the delay of the unit exhibits frequency

and pulse width dependence when operated

beyond the recommended conditions. Please

consult the technical staff at Data Delay Devices

if your application has specific high-frequency

requirements.

Please note that the increment tolerances listed

represent a design goal. Although most delay

increments will fall within tolerance, they are not

guaranteed throughout the address range of the

unit. Monotonicity is, however, guaranteed over

all addresses.

TDISO

TOAX

TAENS

TENIS

PWIN

TDA

PWOUT

TDISH

A7-A0

EN/

OUT

OUT/

Figure 1: Timing Diagram

A i-1

TSKEW

TAIS

Doc #97006

DATA DELAY DEVICES, INC.

1/30/06

Tel: 973-773-2299

Fax: 973-773-9672

http://www.datadelay.com

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