ADP7142AUJZ-3.3-R7 datasheet(21/23 Pages) AD

21 / 23 page

Data Sheet

ADP7142

Rev. H | Page 21 of 23

Figure 66. Example TSOT PCB Layout

Table 8. Recommended LDOs for Very Low Noise Operation

Device

Number

VIN

Range (V)

VOUT

Fixed (V)

VOUT

Adjust

(V)

IOUT

(mA)

IQ at

IOUT

(μA)

IGND-SD

Max

(μA)

Soft

Start

PGOOD

Noise

(Fixed)

10 Hz to

100 kHz

(μV rms)

PSRR

100 kHz

(dB)

PSRR

1 MHz

Package

ADP7102

3.3 to 20

1.5 to 9

1.22 to

300

750

Yes

40 dB

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7104

3.3 to 20

1.5 to 9

1.22 to

500

900

Yes

40 dB

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7105

3.3 to 20

1.8, 3.3, 5

1.22 to

500

900

Yes

40 dB

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7112

2.7 to 20

1.2 to 5

1.2 to 19

200

180

Yes

50 dB

1 mm ×

1.2 mm

6-ball WLCSP

ADP7118

2.7 to 20

1.2 to 5

1.2 to 19

200

180

Yes

50 dB

2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7142

2.7 to 40

1.2 to 5

1.2 to 39

200

180

Yes

50 dB

2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7182

−2.7 to

−28

−1.8 to

−5

−1.22 to

−27

−200

−650

−8

45 dB

2 mm × 2 mm

6-lead LFCSP,

3 mm × 3 mm

8-lead LFCSP,

5-lead TSOT

Table 9. Related Devices

Model

Input Voltage (V)

Output Current (mA)

Package

ADP7118CP

2.7 to 20

200

6-lead LFCSP

ADP7118RD

2.7 to 20

200

8-lead SOIC

ADP7118UJ

2.7 to 20

200

5-lead TSOT

ADP7112CB

2.7 to 20

200

6-ball WLCSP

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