4 Description (continued)

Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-

to-digital converter). Each receiver channel has an analog peak power detector and various digital power

detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for

device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200 MHz

for four RX without FB paths or 600 MHz with two FB paths (1200 MHz BW each).

The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the

device clock.

AFE7906

SBASAF7 – JANUARY 2022

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