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STM32F732IE データシート(PDF) 43 Page - STMicroelectronics

部品番号 STM32F732IE
部品情報  Arm® Cortex®-M7 32b MCUFPU, 462DMIPS, up to 512KB Flash 256164KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
PDF  226 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F732IE データシート(HTML) 43 Page - STMicroelectronics

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DS11854 Rev 6
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STM32F732xx STM32F733xx
Functional overview
47
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDMMC Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller
3.28
Controller area network (bxCAN)
The CAN is compliant with the 2.0A and B (active) specifications with a bit rate
up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive
FIFOs with three stages and 28 shared scalable filter banks (all of them can be used even if
one CAN is used). 256 bytes of SRAM are allocated to the CAN.
3.29
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•
Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
•
12 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Internal FS OTG PHY support
•
HNP/SNP/IP inside (no need for any external resistor)
•
BCD support
For the OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.30
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. The USB OTG HS supports both full-speed and high-speed operations. It
integrates the transceivers for full-speed operation (12 Mbit/s).
The STM32F732xx devices feature a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device
connected to the ULPI is required.



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