SPC58EEX datasheet(109/154 Pages) STMICROELECTRONICS

109 / 154 page

DS11646 Rev 4

109/154

SPC58EEx, SPC58NEx

Electrical characteristics

128

8tHI CC D

SIN Hold Time

SIN hold time

from SCK

CPHA = 0(7)

SCK drive strength

LVDS

0pF

differential

–

1+(P(8) ×tSYS(4))

—ns

SIN hold time

from SCK

CPHA = 1(7)

SCK drive strength

LVDS

0pF

differential

–1

—

9tSUO CC D

SOUT data valid time (after SCK edge)

SOUT data valid

time from SCK

CPHA = 0(9)

SOUT and SCK drive strength

LVDS

15 pF

to 25 pF

differential

—7.0 + tSYS(4)

SOUT data valid

time from SCK

CPHA = 1(9)

SOUT and SCK drive strength

LVDS

15 pF

to 25 pF

differential

—7.0

10 tHO CC D

SOUT data hold time (after SCK edge)

SOUT data hold

time after SCK

CPHA = 0(9)

SOUT and SCK drive strength

LVDS

15 pF

to 25 pF

differential

–7.5 + tSYS(4)

—ns

SOUT data hold

time after SCK

CPHA = 1(9)

SOUT and SCK drive strength

LVDS

15 pF

to 25 pF

differential

–7.5

—

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. LVDS differential load considered is the capacitance on each terminal of the differential pair, as shown in Figure 12.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

tSYS =10 ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV.

8. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to

Table 57. DSPI LVDS master timing — full duplex — modified transfer format

(MTFE = 1), CPHA = 0 or 1 (continued)

Symbol C Characteristic

Condition

Value(1)

Unit

Pad drive

Load

Min

Max

SPC58EEX データシート(PDF) 109 Page - STMicroelectronics

SPC58EEX データシート(HTML) 109 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード

リンク URL

SPC58EEX データシート(PDF) 109 Page - STMicroelectronics

SPC58EEX データシート(HTML) 109 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシート ダウンロード

リンク URL

データシートダウンロード