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SPC58EEX データシート(PDF) 113 Page - STMicroelectronics |
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SPC58EEX データシート(HTML) 113 Page - STMicroelectronics |
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113 / 154 page  DS11646 Rev 4 113/154 SPC58EEx, SPC58NEx Electrical characteristics 128 Figure 35. DSPI LVDS and CMOS master timing–output only— MTFE = 1, CHPA = 1 3.18.2.2 Slave mode timing 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays. 4. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 5. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. PCSx SCK Output SOUT First Data Data Last Data (CPOL = 0) tSUO tHO tCSV tSDC tSCK tCSH Table 60. DSPI CMOS slave timing — full duplex — normal and modified transfer formats (MTFE = 0/1) # Symbol C Characteristic Condition Min Max Unit Pad Drive Load 1tSCK CC D SCK Cycle Time(1) —— 62 — ns 2tCSC SR D SS to SCK Delay(1) —— 16 — ns 3tASC SR D SCK to SS Delay(1) —— 16 — ns 4tSDC CC D SCK Duty Cycle(1) —— 30 — ns 5tA CC D Slave Access Time(1) (2) (3) (SS active to SOUT driven) Very strong 25 pF — 50 ns Strong 50 pF — 50 ns Medium 50 pF — 60 ns 6tDIS CC D Slave SOUT Disable Time(1) (2) (3) (SS inactive to SOUT High- Z or invalid) Very strong 25 pF — 5 ns Strong 50 pF — 5 ns Medium 50 pF — 10 ns |
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