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ADCMP604 データシート(PDF) 19 Page - Analog Devices

部品番号 ADCMP604
部品情報  Four-Channel Transimpedance Amplifier with Output Multiplexing
PDF  34 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADCMP604 データシート(HTML) 19 Page - Analog Devices

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LTC6563
19
Rev. 0
For more information www.analog.com
Output Offset and Current Control
The output stage of the LTC6563 has many options. The
ADJ1 and ADJ0 pins provide four options for the output
current drive. The output voltage swing is dependent on
the adjust setting, the external differential termination
resistor, and the Tilt input. The purpose of the Tilt input is
to offset the DC output voltages, thereby increasing the
full output swing of the TIA for unipolar inputs. Output
TILT is essential for the ADC as the input from the pho-
todetector is unipolar. To maximize the input swing of
the ADC, the DC value of OUT is offset low while the DC
value of OUT is offset high. This allows the LTC6563 to
maximize the full dynamic range of the ADC. These pins
should be connected to low noise inputs.
LTC6563 transimpedance gain (RT) consists of the over-
all gain from the multi-stages involved in producing the
output for a given input current. The output is differential
and ½ RT is achieved if only one of the outputs is utilized.
It is possible to change the transimpedance gain (RT)
by changing RL_EXT as shown in Table 1, and Table 2.
Also, since the ADJ pins respond in less than 100ns,
these pins can be used for on the fly gain switching if the
application needs that. An example would be to reduce
the TIA gain if an overly strong signal is received by the
LTC6563. It’s important to note the following regarding
gain adjustment:
• The linear input current range (40µA with no Tilt, 90µA
with full Tilt) is not affected by these changes.
• RLDIFF refers to the total load seen by the differential
output(s) whereas RL_EXT is the external differential
load. Refer to Figure 17 to Figure 19 to see examples
of various external single-ended load (50Ω, 75Ω, and
100Ω) illustrated.
APPLICATIONS INFORMATION
Table 1. Output Stage when Tilt Pin = 0V, OUT Connected to TERM and OUT Connected to TERM1
IIN (µA)
ADJ1
ADJ0
OUT (mA)
OUTBAR (mA)
RT (Ω)
RL_EXT = 100Ω DIFF
RT (Ω)
RL_EXT = 200Ω DIFF
RT (Ω)
RL_EXT = OPEN
0
0
0
7
7
5.55k
7.4k
11.1k
0
1
14
14
11.1k
14.8k
22.2k
1
0
21
21
16.65k
22.2k
33.3k
1
1
28
28
22.2k
29.6k
44.4k
45
0
0
12
2
5.55k
7.4k
11.1k
0
1
24
4
11.1k
14.8k
22.2k
1
0
36
6
16.65k
22.2k
33.3k
1
1
48
8
22.2k
29.6k
44.4k
1 Output voltage compliance to be observed at higher RL_EXT and higher ADJ settings.
Table 2. Output Stage when Tilt Pin = VCC, OUT Connected to TERM and OUT Connected to TERM1
IIN (µA)
ADJ1
ADJ0
OUT (mA)
OUTBAR (mA)
RT (Ω)
RL_EXT = 100Ω DIFF
RT (Ω)
RL_EXT = 200Ω DIFF
RT (Ω)
RL_EXT = OPEN
0
0
0
2
12
5.55k
7.4k
11.1k
0
1
4
24
11.1k
14.8k
22.2k
1
0
6
36
16.65k
22.2k
33.3k
1
1
8
48
22.2k
29.6k
44.4k
90
0
0
12
2
5.55k
7.4k
11.1k
0
1
24
4
11.1k
14.8k
22.2k
1
0
36
6
16.65k
22.2k
33.3k
1
1
48
8
22.2k
29.6k
44.4k
1 Output voltage compliance to be observed at higher RL_EXT and higher ADJ settings.



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