LTM4650 datasheet(21/28 Pages) AD

21 / 28 page

LTM4660

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

4660 F12

Figure 12. Thermal Image 48V to 12V, 25A; 200LFM Airflow; No

Heat Sink (Based on 6-Layer PCB with 2oz Copper on All Layers)

• Place a dedicated power ground layer underneath

the unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put via directly on the pad unless they are

capped or plated over.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. SGND is connected

to GND internal to the module.

• For parallel modules, tie the VOUT, VFB, and COMP pins

together. Use an internal layer to closely connect these

pins together. The TRACK pin can be tied a common

capacitor for regulator soft-start.

• Bring out test points on the signal pins for monitoring.

Figure 13 gives a good example of the recommended

layout for input, output, CFLY and CMID capacitors on the

top layer. Pinout of LTM4660 is designed such that CFLY

capacitors can be conveniently placed on the bottom

layer right underneath the module, with minimal impact

to total PCB area. (See Figure 14 for example of bottom

layer layout).

C D

G H

L M

4660 F13

COUT2

COUT1

VOUT

GND

VIN

CIN1

CIN2

CFLY

C–

C+

CMID

GND

MID

Figure 13. Recommended Layout for Top Layer

C+

GND

4660 F14

C–

CMID

GND

MID

C D

G H

L M

CFLY

Figure 14. Recommended Layout for Bottom Layer

LTM4650 データシート(PDF) 21 Page - Analog Devices

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