ART2K0FE_2K0FES_2K0FEG

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Product data sheet

Rev. 4 — 22 March 2022

11 of 18

ART2K0FE(S)(G)

Power LDMOS transistor

8.

Package outline

Fig 11. Package outline SOT539AN

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

SOT539AN

sot539an_po

20-04-20

mm

max

nom

min

4.7

4.2

11.81

11.56

31.55

30.94

31.52

30.96

9.5

9.3

9.53

9.27

1.75

1.50

17.12

16.10

3.48

2.97

10.29

10.03

0.51

A

Dimensions

Flanged balanced ceramic package; 2 mounting holes; 4 leads

SOT539AN

bc

0.18

0.10

e

13.72

FH

25.53

25.27

41.28

41.02

inches

max

nom

min

0.185

0.165

0.465

0.455

1.242

1.218

1.241

1.219

0.374

0.366

0.375

0.365

0.069

0.059

0.674

0.634

0.137

0.117

3.30

3.05

p

0.130

0.120

2.26

2.01

Q

0.089

0.079

0.405

0.395

0.02

0.25

0.01

35.56

1.400

0.25

0.01

0.007

0.004

0.54

1.005

0.995

1.625

1.615

Note

1. millimeter dimensions are derived from the original inch dimensions.

2. recommended screw pitch dimension of 1.52 inch (38.6 mm) based on M3 screw.

3. ceramic window frame has a minimum thickness of 0.400 mm.

0

5

10 mm

scale

p

A

F

b

e

D

U2

L

H

Q

c

5

12

4

3

D1

E

A

w1

AB

M

M

M

q

U1

H1

C

B

M

M

w2

C

E1

M

w3

X

(note 3)

detail X