P60C080 datasheet(2/12 Pages) NXP

2 / 12 page

SMX2_FAM_P60D080_D144_SDS

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Objective short data sheet

PUBLIC

Rev. 1 — 21 October 2010

198210

2 of 12

NXP Semiconductors

P60C080 and P60C144

Secure high-performance contact interface smart card controller

General description

The P60C080 and P60C144 devices are members of the new SmartMX2 Family and offer

with their two different EEPROM size variations a common set of functional blocks and

interfaces, supporting high-performance, high-security contact applications. Figure 1

shows the block diagram of the modular controller architecture consisting of the following

blocks and features:

• SmartMX2 CPU with enhanced application instruction set supporting 32-/24-/16-/8-bit

move, logical and arithmetic functions

• Fame2 coprocessor based on innovative power-efficient and fast architecture for

optimized RSA/ECC cryptography

• SBC coprocessor interface with multiple data/key register sets now supporting both

AES and Triple-DES

• ISO/IEC 7816 data transfer improved with enhanced protocol support for T=0 and

T=1 protocols

• New Copy Machines supporting direct memory access (DMA) to memories and all

SFRs

• Cyclic Redundancy Check (CRC) coprocessors 16-bit/32-bit

• Memory Management Unit (MMU) with 16 cache segments

• New security features especially targeting combined laser light attacks and integrity of

code execution and data fetch

• Development tool suite based on approved suppliers Keil and Ashling

–

μVision4 user interface

– New and high-performance emulation hardware “SmartICE series”

• High-memory SoftMasking device for code development purposes

• Common Criteria security certified high-performance crypto library supporting various

algorithms

• Consequent family concept with regard to all future platforms of the P60 family

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