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VSC8540XMVRT-MQ データシート(PDF) 25 Page - Microchip Technology |
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VSC8540XMVRT-MQ データシート(HTML) 25 Page - Microchip Technology |
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25 / 87 page  2022 Microchip Technology Inc. and its subsidiaries DS60001603E-page 25 VSC8540RT FIGURE 5-10: INLINE-POWERED ETHERNET SWITCH DIAGRAM The following procedure describes the steps that an Ethernet switch must perform to process inline-power requests made by a link partner that is, in turn, capable of receiving inline-power: 1. Enable the inline-powered device detection mode on each VSC8540RT PHYs using its serial management inter- face. Set register bit 23E1.10 to 1. 2. Ensure that the auto-negotiation enable bit (register 0.12) is also set to 1. In the application, the device sends a special fast link pulse signal to the link partner. Reading register bit 23E1.9:8 returns 00 during the search for devices that require Power-over-Ethernet (PoE). 3. The VSC8540RT PHYs monitor their inputs for the fast link pulse signal looped back by the link partner. A link partner capable of receiving PoE loops back the fast link pulses when the link partner is in a powered down state. This is reported when register bit 23E1.9:8 reads back 01. It can also be verified as an inline-power detection interrupt by reading register bit 26.9, which should be a 1, and which is subsequently cleared and the interrupt de-asserted after the read. When a link partner device does not loop back the fast link pulse after a specific time, register bit 23E1.9:8 automatically resets to 10. 4. If the VSC8540RT PHYs report that the link partner requires PoE, the Ethernet switch must enable inline-power on this port, independent of the PHY. 5. The PHY automatically disables inline-powered device detection when the register bits 23E1.9:8 automatically reset to 10, and then automatically changes to its normal auto-negotiation process. A link is then autonegotiated and established when the link status bit is set (register bit 1.2 is set to 1). 6. In the event of a link failure (indicated when register bit 1.2 reads 0), it is recommended that the inline-power be disabled to the inline-powered device independent of the PHY. The VSC8540RT PHY disables its normal auto- negotiation process and re-enables its inline-powered device detection mode. 5.7 IEEE 802.3af Power-over-Ethernet Support The VSC8540RT device is compatible with designs intended for use in systems that supply power to data terminal equipment (DTE) by means of the MDI or twisted pair cable, as described in IEEE 802.3af Clause 33. SMI Control Processor PHY_port1 MAC Interface Inline, Power-over-Ethernet (PoE) Power Supply Cat5 Fast Ethernet Switch PHY_port0 PHY_portn Transformer RJ-45 I/F Transformer RJ-45 I/F Transformer RJ-45 I/F Link Partner Link Partner Link Partner |
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