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SWCS049D データシート(PDF) 14 Page - Texas Instruments |
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SWCS049D データシート(HTML) 14 Page - Texas Instruments |
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14 / 144 page  14 TPS65911 SWCS049S – JUNE 2010 – REVISED AUGUST 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65911 Specifications Copyright © 2010–2018, Texas Instruments Incorporated (1) The internal pullups on the CTL-I2C and SR-I2C pins are used for test purposes or when the SR-I2C interface is not used. Discrete pullups to the VIO supply must be mounted on the board in order to use the I2C interfaces. The internal I2C pullups must not be used for functional applications. 5.5 Electrical Characteristics: I/O Pullup and Pulldown Over operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1 external pullup resistor Connected to VDDIO 1.2 kΩ SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1 programmable pullup (DFT, default inactive) Grounded, VDDIO = 1.8 V –45% 8 45% kΩ SLEEP, PWRHOLD, programmable pulldown (default active) At 1.8 V, VRTC = 1.8 V 2 4.5 10 µA NRESPWRON, NRESPWRON2 pulldown At 1.8 V, VCC7 = 5.5 V, OFF state 2 4.5 10 µA 32KCLKOUT pulldown (disabled in ACTIVE-SLEEP state) At 1.8 V, VRTC = 1.8 V, OFF state 2 4.5 10 µA PWRON programmable pullup (default active) Grounded, VCC7 = 5.5 V –40 –31 –15 µA GPIO0-8 programmable pulldown (default active except GPIO0) At 1.8 V, VRTC = 1.8 V, OFF state 2 4.5 10 µA GPIO0-8 external pullup resistor Connected to VDDIO –20% 120 20% kΩ HDRST programmable pulldown (default active) At 1.8 V, VRTC = 1.8 V 2 4.5 10 µA 5.6 Electrical Characteristics: Digital I/O Voltage Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RELATED I/Os: PWRON Low-level input voltage (VIL) 0.3 × VBAT V High-level input voltage (VIH) 0.7 × VBAT V RELATED I/Os: PWRHOLD, GPIO0-8, PWRDN Low-level input voltage (VIL) 0.45 V High-level input voltage (VIH) 1.3 VBAT V RELATED I/Os: BOOT1 Low level input – Impedance between BOOT1 and GND 10 kΩ High level input – Impedance between BOOT1 and VRTC 10 kΩ HiZ level input – Impedance between BOOT1 and GND 500 kΩ RELATED I/Os: SLEEP Low-level input voltage (VIL) 0.35 × VDDIO V High-level input voltage (VIH) 0.65 × VDDIO V RELATED I/Os: HDRST Low-level input voltage (VIL) 0.35 × VRTC V High-level input voltage (VIH) 0.65 × VRTC V RELATED I/Os: NRESPWRON, INT1, 32KCLKOUT Low-level output voltage (VOL) IOL = 100 µA 0.2 V IOL = 2 mA 0.45 |
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