28 GHz 5G Medium Power Amplifier (MPA)

CMX90A702

© www.cmlmicro.com

Page 15

D/90A702/1 June 2022

Thermal Design

The primary RF/DC ground and thermal path is via the exposed die pad on the back side of the package, which must

be connected to the PCB ground plane. An array of plated and copper filled through-hole vias directly underneath the

die pad area is needed to conduct heat away and minimise ground inductance. The PCB layout should provide a

thermal radiator appropriate for the intended operation, adding as much copper to inner and outer layers as possible

to avoid excessive junction temperature.

Device junction temperature (Tj) can be calculated using Tj = Tc + (Pdiss x Rjc) where Pdiss = Pdc + Pin – Pout and Tc is

the case temperature on the backside of the package (die pad) in contact with the PCB.

Bias Procedure

The CMX90A702 is a three-stage enhancement mode amplifier and therefore requires positive gate voltage to set the

quiescent drain currents. Stages 1 and 2 have common gate and drain connections and Stage 3 has separate gate and

drain connections.

Power-up:

-

Connect the amplifier in a 50Ω environment, with no RF input.

-

Ensure the gate voltages (Vg12 and Vg3) are set to 0 V.

-

Apply drain supplies (Vd12 and Vd3) at 4V.

-

Increase Vg12 to set Id12 to 73 mA (Vg12 ~ 0.415 V).

-

Increase Vg3 to set Id3 to 109 mA (Vg3 ~ 0.415 V).

-

A suitable RF input can now be applied.

Power -down:

-

Turn off the applied RF input.

-

Decrease Vg12 and Vg3 to 0 V.

-

Switch off drain supplies (Vd12 and Vd3).

-

Switch off Vg12 and Vg3.

RFin

RFin (pin 3) is internally matched to 50 Ω. Note that at DC this pin is resistive to ground (approximately 50 Ω) and

therefore DC voltages should not be applied to this pin.

RFout

RFout (pin 13) is internally matched to 50 Ω and DC blocking with an integrated blocking capacitor.

Vd12 and Vd3

The drain supply pins are replicated on both sides of the device and are connected internally. The drain connections

only need to be made to one side, therefore for Vd12 either pin 8 or pin 19 can be used for stages 1 and 2. For Vd3

either pin 10 or pin 17 can be used for stage 3.

Vg12, Vg3 and PA_OFF

When PA_OFF (pin 5) is connected to ground, the gate voltages pass through the control circuit on to their relevant

stages. When PA_OFF (pin 5) is high (nominally 2.5V), the gates voltages are disconnected from the stage gates which

are also shorted to ground.