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WM8940CGEFL/V データシート(PDF) 48 Page - Cirrus Logic

部品番号 WM8940CGEFL/V
部品情報  Mono CODEC with Speaker Driver
PDF  88 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8940CGEFL/V データシート(HTML) 48 Page - Cirrus Logic

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WM8940
48
Rev 4.4
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to AVDD/2 through a resistor.
This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage
buffer and the output pins can be controlled using the VROI control bit. The default impedance is low,
so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired
for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30k
.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R49
0
VROI
0
VREF (AVDD/2) to analogue output
resistance
0: approx 1k
1: approx 30 k
Table 39 Disabled Outputs to VREF Resistance
A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This
buffer can be enabled using the BUFIOEN register bit.
Table 40 summarises the tie-off options for the speaker and mono output pins.
AVDD/2
-
+
AVDD/2
Used to tie off all unused
inputs and outputs
BUFIOEN
R1[2]
SPKOUTP
SPKOUTN
MONOOUT
1k
30k
VROI
R49[0]
1k
30k
VROI
R49[0]
1k
30k
VROI
R49[0]
Figure 21 Unused Input/Output Pin Tie-off Buffers
MONOEN/
SPKN/PEN
VROI
OUTPUT CONFIGURATION
0
0
1k
Ω tieoff to AVDD/2
0
1
30k
Ω tieoff to AVDD/2
1
X
Output enabled (DC level=AVDD/2)
Table 40 Unused Output Pin Tie-off Options



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