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ZMOD4450AI2 データシート(PDF) 14 Page - Renesas Technology Corp |
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ZMOD4450AI2 データシート(HTML) 14 Page - Renesas Technology Corp |
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14 / 22 page ![]() ZMOD4450 Datasheet © 2021 Renesas Electronics Corporation 14 June 30, 2021 Figure 6. Bus Timing Table 9. Bus Timing Characteristics Symbol Parameter Standard Mode Fast Mode Units fSCL Maximum SCL clock frequency 100 400 kHz tHDSTA Minimum START condition hold time relative to SCL edge 4 µs tLOW Minimum SCL clock LOW width 4.7 µs tHIGH Minimum SCL clock HIGH width 4 µs tSUSTA Minimum START condition setup time relative to SCL edge 4.7 µs tHDDAT Minimum data hold time on SDA relative to SCL edge 0 µs tSUDAT Minimum data setup time on SDA relative to SCL edge 0.1 0.1 µs tSUSTO Minimum STOP condition setup time on SCL 4 µs tBUS Minimum bus free time between stop condition and start condition 4.7 µs SDA SCL tHDSTA tLOW tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSUSTO tBUS |
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