DVR datasheet(81/416 Pages) MICROCHIP

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DS30010118D-page 81

PIC24FJ256GA705 FAMILY

TABLE 7-1:

RESET FLAG BIT OPERATION

bit 5

SWDTEN: Software Enable/Disable of WDT bit(4)

1 = WDT is enabled

0 = WDT is disabled

bit 4

WDTO: Watchdog Timer Time-out Flag bit(1)

1 = WDT time-out has occurred

0 = WDT time-out has not occurred

bit 3

SLEEP: Wake from Sleep Flag bit(1)

1 = Device has been in Sleep mode

0 = Device has not been in Sleep mode

bit 2

IDLE: Wake-up from Idle Flag bit(1)

1 = Device has been in Idle mode

0 = Device has not been in Idle mode

bit 1

BOR: Brown-out Reset Flag bit(1)

1 = A Brown-out Reset has occurred (also set after a Power-on Reset)

0 = A Brown-out Reset has not occurred

bit 0

POR: Power-on Reset Flag bit(1)

1 = A Power-on Reset has occurred

0 = A Power-on Reset has not occurred

Flag Bit

Setting Event

Clearing Event

TRAPR (RCON<15>)

Trap Conflict Event

POR

IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access

POR

CM (RCON<9>)

Configuration Mismatch Reset

POR

EXTR (RCON<7>)

MCLR Reset

POR

SWR (RCON<6>)

RESET Instruction

POR

WDTO (RCON<4>)

WDT Time-out

CLRWDT, PWRSAV Instruction, POR

SLEEP (RCON<3>)

PWRSAV #0 Instruction

POR

IDLE (RCON<2>)

PWRSAV #1 Instruction

POR

BOR (RCON<1>)

POR, BOR

—

POR (RCON<0>)

POR

—

Note:

All Reset flag bits may be set or cleared by the user software.

RCON: RESET CONTROL REGISTER (CONTINUED)

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN

bit has no effect. Retention mode preserves the SRAM contents during Sleep.

3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep.

Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.

4: If the FWDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless

of the SWDTEN bit setting.

5: The BOREN<1:0> (FPOR<1:0>) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect.

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