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DVR30 データシート(PDF) 36 Page - Microchip Technology |
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DVR30 データシート(HTML) 36 Page - Microchip Technology |
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36 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 36 2016-2018 Microchip Technology Inc. FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register RCOUNT REPEAT Loop Counter Register CORCON CPU Control Register DISICNT Disable Interrupt Count Register DSRPAG Data Space Read Page Register DSWPAG Data Space Write Page Register Instruction Decode and Control PCH 16 Program Counter 16-Bit ALU 23 23 24 23 Data Bus Instruction Reg 16 Divide Support 16 EA MUX RAGU WAGU 16 16 8 Interrupt Controller Stack Control Logic Loop Control Logic Data Latch Data RAM Address Latch Control Signals to Various Blocks Program Memory/ Data Latch Address Bus 16 16 16 Hardware Multiplier 16 To Peripheral Modules Address Latch Up to 0x7FFF Extended Data Space PCL 16 x 16 W Register Array EDS and Table Data Access Control Block ROM Latch |
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