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U637256
7
March 31, 2006
STK Control #ML0054
Rev 1.0
Nonvolatile Memory Operations
Mode Selection
E
W
A13 - A0
(hex)
Mode
I/O
Power
Note
s
H
X
X
Not Selected
Output High Z
Standby
L
H
X
Read SRAM
Output Data
Active
m
L
L
X
Write SRAM
Input Data
Active
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
k:
The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l:
While there are 15 addresses on the U637256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G
≤ V
IL.
No.
PowerStore
Power Up RECALL
Symbol
Conditions
Min.
Max.
Unit
Alt.
IEC
24
Power Up RECALL Durationn
tRESTORE
650
μs
25
STORE Cycle Durationf, e
tPDSTORE
10
ms
26
Time allowed to Complete SRAM
Cyclef
tDELAY
1
μs
Low Voltage Trigger Level
VSWITCH
4.0
4.5
V
n:
tRESTORE starts from the time VCC rises above VSWITCH.
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