STA8100GA datasheet(13/42 Pages) STMICROELECTRONICS

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DS13006 Rev 4

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STA8100GA

General description

3.2

RF front end (G5RF)

The integrated RF front-end is able to support different bands (L1, L2, L5, and E6) thanks to

a programmable and flexible RF-IF chain driven by a fractional PLL.

The RF_IF chain is followed by a 3-bit ADC able to convert the IF signal to Sign (SIGN) and

Magnitude (MAG1, MAG0) bit. The MAG bit is internally integrated in order to control the

variable gain amplifiers.

The embedded fractional PLL allows supporting a wide range of reference clocks (10 to

55 MHz).

3.3

Multi-band multi-constellation base band (G5BB) processor

STA8100GA integrates G5BB proprietary IP, which is the STMicroelectronics latest

generation high-sensitivity baseband processor fully compliant with all different

constellations and bands: GPS, Galileo, Glonass, BeiDou, NAVIC (former IRNSS) and

QZSS systems.

3.4

MCU sub system

The Cortex® M7 core masters the system resources (memories, registers, and external

memory controllers) through the AXI, AHB and APB interconnections present in the SOC.

3.4.1

Caches

The size of the instruction and data cache used for ARM® sub-system in STA8100GA is

16 KB each.

3.4.2

TCM

ARM® Cortex® M7 has a TCM Control Unit (TCU) with TCM interfaces and an AHB slave

(AHBS) interface for system access to TCMs. These TCM memories are integrated outside

the ARM® sub-system. STA8100GA has a 64 KB ITCM memory and 384 KB of DTCM

memory.

In the DTCM memory 160 KB is dedicated for ARM® usage and the remaining 224 KB

DTCM is shared between the ARM® sub-system and the G5BB module.

ARM® provides access to the TCM memories through an AHB slave interface. This AHBS

interface is connected to the AMBA infrastructure in STA8100GA so that DMA present on

the bus can access the TCM memories MCU.

3.4.3

Nested Vector Interrupt Controller (NVIC)

This Nested Vectored Interrupt Controller (NVIC) allows the operative system interrupt

handler to quickly dispatch interrupt service routines in response to peripheral interrupts. It

provides a software interface to the interrupt system. ARM® Cortex® M7 has an NVIC

module for handling the interrupts. The NVIC supports 128 interrupts with 16 levels of

priority, which can be changed dynamically. The software can control each request line to

generate software interrupts.

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