List of figures

Figure 1.

Pin connections (top view) ............................................................ 2

Figure 2.

Block diagram .................................................................... 3

Figure 3.

ON-resistance vs. S or D voltage for different power supply voltage............................... 11

Figure 4.

ON-resistance vs. power supply voltage.................................................. 11

Figure 5.

ON-resistance vs. S or D voltage for VDD / VSS = 4.5 V/0 V .................................... 11

Figure 6.

ON-resistance vs. S or D voltage for VDD / VSS = 5 V/0 V...................................... 11

Figure 7.

ON-resistance vs. S or D voltage for VDD/ VSS = 3 V/-8 V...................................... 12

Figure 8.

ON-resistance vs. S or D voltage for VDD/ VSS = 3 V/-12 V..................................... 12

Figure 9.

ON-resistance vs. S or D voltage for VDD/ VSS = 5 V/-10.5 V ................................... 12

Figure 10.

IDD vs. logic voltage at 25 °C, VSelect swept for two switches, the two others left grounded ............... 12

Figure 11.

ISS vs. logic voltage at 25 °C, VSelect swept for two switches, the two others left grounded ............... 13

Figure 12.

IDD vs. logic voltage at -40 °C, VSelect swept for two switches, the two others left grounded .............. 13

Figure 13.

ISS vs. logic voltage at -40 °C, VSelect swept for two switches, the two others left grounded............... 13

Figure 14.

IDD vs. logic voltage at 125 °C, VSelect swept for two switches, the two others left grounded .............. 13

Figure 15.

ISS vs. logic voltage at 125 °C, VSelect swept for two switches, the two others left grounded .............. 14

Figure 16.

Leakage currents at 25 °C ........................................................... 14

Figure 17.

Leakage currents at -40 °C .......................................................... 14

Figure 18.

Leakage currents at 125 °C .......................................................... 14

Figure 19.

TONS1(SEL) vs. temperature.......................................................... 15

Figure 20.

TONS2(SEL) vs. temperature.......................................................... 15

Figure 21.

TOFFS1(SEL) vs. temperature ......................................................... 15

Figure 22.

TOFFS2(SEL) vs. temperature ......................................................... 15

Figure 23.

Bandwidth ...................................................................... 15

Figure 24.

OFF isolation .................................................................... 15

Figure 25.

Crosstalk ....................................................................... 16

Figure 26.

Input threshold voltage test circuit ...................................................... 17

Figure 27.

Input threshold ................................................................... 17

Figure 28.

Control input leakage current test circuit.................................................. 17

Figure 29.

ON-resistance, flatness and mismatch test circuit ........................................... 17

Figure 30.

OFF and ON leakage currents test circuit................................................. 17

Figure 31.

OFF leakage current test circuit ....................................................... 17

Figure 32.

Propagation delay test circuit ......................................................... 18

Figure 33.

Propagation delay timing ............................................................ 18

Figure 34.

Turn-on time, turn-off time and skew on SEL pin and charge injection test circuit...................... 18

Figure 35.

Turn-on time and turn-off time on SEL pin timing ............................................ 18

Figure 36.

Charge injection timing ............................................................. 18

Figure 37.

Turn-on time, turn-off time on INH pin test circuit ............................................ 18

Figure 38.

Turn-on time, turn-off time on INH pin timing............................................... 19

Figure 39.

Break before make test circuit......................................................... 19

Figure 40.

Break before make timing ........................................................... 19

Figure 41.

OFF isolation test circuit ............................................................ 19

Figure 42.

Crosstalk test circuit ............................................................... 19

Figure 43.

Bandwidth test circuit............................................................... 19

Figure 44.

CSON test circuit .................................................................. 20

Figure 45.

CSOFF test circuit ................................................................. 20

Figure 46.

CDON test circuit .................................................................. 20

Figure 47.

QFN20 (4x4 mm) package outline ...................................................... 22

Figure 48.

QFN20 (4x4 mm) recommended footprint ................................................ 23

STG1218

List of figures

DS13729 - Rev 3

page 28/29