MOSA

MS6260

Gain And Attenuation Volume Controller IC

REV 1

5

www.mosanalog.com.tw

FREQUENCY (Hz)

FREQUENCY (Hz)

FREQUENCY (Hz)

PSRR vs. frequency

PSRR vs. frequency

PSRR vs. frequency

CAP=22uF

CAP=22uF

CAP=22uF

CAP=10uF

CAP=10uF

CAP=10uF

CAP=2.2uF

CAP=2.2uF

CAP=2.2uF

I

Start and stop conditions

A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop

condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing

diagram below.

SDA

SCL

Start

Stop

SCL : Serial Clock Line, SDA : Serial Data Line

Data validity

A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and

LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.

SDA

SCL

Data line

stable,

Data valid

Data

change

allowed

Byte format

Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit.

The MSB is transmitted first.