SM8521 datasheet(13/56 Pages) SHARP

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SM8521

- 13 -

76543210

MSB

LSB

MSB

Upper 8-bit

LSB

Lower 8-bit

Address

High

Low

Data Format

0000H-00FFH

Even byte, 0000H-00FEH,

following byte (odd byte)

0000H-00FFH

Bit

Byte

Word

BCD

Data

Type

Upper BCD digit

Lower BCD digit

0000H-00FFH or FF00H-FFFFH

0000H-00FFH

0000H-00FFH or FF00H-FFFFH

(Under shorthand)

0000H-FFFEH

following byte

0000H-00FFH

Memory address

Fig. 3

Address Space

The SM85CPU has a 64 k-byte address space,

which is divided into RAM (0000H-0FFFH) and ROM

(1000H-FFFFH) areas. The address 0000H-007FH

are both shared by RAM and register file. Fig. 9-1

shows the SM8521 Memory Map.

The RAM and register file allocated at 0000H-007FH

can

selected

the

addressing

mode

designated by instructions.

The SM8521 supports an Memory Management

Unit used to external memory area expantion.

Refer to "Memory Management Unit (MMU)".

ROM Area

ROM area starts at the address 1000H of the space

address. The first portion (1000H-101FH) is reserved

for the interrupt vector table. Each 2 bytes entry in

the vector table contains the address of interrupts.

When an interrupt encountered, the CPU jumps to

the corresponding branch address of vector table

for program executing. The address 1020H marks

the start of the user program area itself. Executing

always starts at 1020H after hardware reset.

The register file is allocated between 0000H and

007FH. The first 16 bytes (0000H-000FH) area are

general registers. The remainder is for CPU control

registers, peripherals control register and data

RAM Area

The RAM area starts at the beginning 0000H of the

address space. It overlaps the register file for the

address 0000H-007FH.

This arrangement is to shorten the instruction

length as much as possible and to permit the use

with both RAM and the register file for faster

execution.

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