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LT1950

sn1950 1950fs

APPLICATIO S I FOR ATIO

Programming Leading Edge Blank Time

For PWM controllers driving external MOSFETs, noise can

be generated during GATE rise time due to various para-

sitic effects. This noise can disturb the input to the current

sense comparator (ISENSE) and cause premature turn-off

of the external MOSFET. The LT1950 provides program-

mable leading edge blanking of the current sense com-

parator to avoid this effect.

Blanking is provided in 2 phases: The first phase is during

GATE rise time. GATE rise times vary depending on

MOSFET type. For this reason the LT1950 automatically

blanks the current comparator output until the “leading

edge” of the GATE is detected. This occurs when the GATE

voltage has risen within 0.5V of the output driver supply

(VIN2) or has reached its clamp level of 13V. The second

phase of blanking starts immediately after “leading edge”

has been detected. This phase is programmable using a

resistor (RBLANK) from the BLANK pin to ground. Typical

values for this portion of the blanking period are 110ns at

RBLANK = 0Ω up to 290ns at RBLANK = 75k. Figure 8 shows

blanking vs RBLANK. Blanking duration can be approxi-

mated as:

BLANKING EXTENDED

BLANK

()

•









110

Figure 8. Blanking Timing Diagram

1950 F04

RBLANK = 0Ω

Ω < RBLANK < = 75k

60ns

(AUTOMATIC)

LEADING

EDGE

BLANKING

(DEFAULT)

EXTENDED

BLANKING

(PROGRAMMABLE)

EXTENDED

BLANKING

CURRENT

SENSE

DELAY

GATE

BLANKING

Xns

(X + 110)ns

[X + 110 + (60 • RBLANK/25k)]ns

Programming Volt-Second Clamp

The VSEC pin is used to provide an adaptive maximum duty

cycle clamp for sophisticated control of the simplest

forward converter topology (single primary-side switch).

This adaptive maximum duty cycle clamp allows the use of

the smallest transformers, MOSFETs and output rectifiers

by addressing the biggest concern in single switch for-

ward converter topologies - transformer reset. The sec-

tion “Application Circuits-Forward Converter Applications”

covers transformer reset requirements and highlights the

advantages of the LT1950 adaptive maximum duty cycle

clamp. The programmable maximum duty cycle clamp is

controlled by the voltage on the VSEC pin. As voltage on the

VSEC pin increases within a specified range, maximum

duty cycle decreases. By deriving VSEC pin voltage from

the system input supply, a volt-second clamp is realized.

Maximum GATE output duty cycle follows a 1/X relation-

ship given by (105/VSEC)%. (see Maximum Duty Cycle vs

VSEC Voltage graph in the Typical Performance Character-

istics section). For example, if the minimum input supply

for a forward converter application is 36V, the VSEC pin can

be programmed with a maximum duty cycle of 75% at

1.4V. A movement of input voltage to 72V will lift the VSEC

pin to 2.8V, resulting in a maximum duty cycle of 37.5%.

As the section on Forward Converter Applications will

show, transformer reset requirements are met with the

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