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STM32H753II データシート(PDF) 49 Page - STMicroelectronics

部品番号 STM32H753II
部品情報  32-bit Arm® Cortex®-M7 480MHz MCUs, 2MB Flash,1MB RAM, 46 com. and analog interfaces, crypto
PDF  361 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
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STM32H753II データシート(HTML) 49 Page - STMicroelectronics

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DS12117 Rev 8
49/360
STM32H753xI
Functional overview
53
3.36
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.37
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
Full-duplex communication mode
automatic SWP bus state management (active, suspend, resume)
configurable bitrate up to 2 Mbit/s
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.



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