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STM32L010C6 データシート(PDF) 79 Page - STMicroelectronics

部品番号 STM32L010C6
部品情報  Value line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0,32-Kbyte Flash memory, 8-Kbyte SRAM, 256-byte EEPROM, ADC
PDF  89 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L010C6 データシート(HTML) 79 Page - STMicroelectronics

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DS12324 Rev 3
79/89
STM32L010C6
Electrical characteristics
81
Table 59. SPI characteristics in voltage Range 3 (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
--
2
MHz
Slave mode
2(2)
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
%
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4Tpclk
-
-
ns
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk - 2
Tpclk
Tpclk + 2
tsu(MI)
Data input setup time
Master mode
3
-
-
tsu(SI)
Slave mode
3
-
-
th(MI)
Data input hold time
Master mode
16
-
-
th(SI)
Slave mode
14
-
-
ta(SO
Data output access time
Slave mode
30
-
70
tdis(SO)
Data output disable time
Slave mode
40
-
80
tv(SO)
Data output valid time
Slave mode
-
26.5
47
Master mode
-
4
6
tv(MO)
Data output hold time
Slave mode
20
-
-
th(SO)
Master mode
3
-
-
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.



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