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74ALS175D データシート(PDF) 4 Page - NXP Semiconductors

部品番号 74ALS175D
部品情報  Quad D flip-flop
PDF  8 Pages
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メーカー  PHILIPS [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALS175D データシート(HTML) 4 Page - NXP Semiconductors

  74ALS175D Datasheet HTML 1Page - NXP Semiconductors 74ALS175D Datasheet HTML 2Page - NXP Semiconductors 74ALS175D Datasheet HTML 3Page - NXP Semiconductors 74ALS175D Datasheet HTML 4Page - NXP Semiconductors 74ALS175D Datasheet HTML 5Page - NXP Semiconductors 74ALS175D Datasheet HTML 6Page - NXP Semiconductors 74ALS175D Datasheet HTML 7Page - NXP Semiconductors 74ALS175D Datasheet HTML 8Page - NXP Semiconductors  
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Philips Semiconductors
Product specification
74ALS175
Quad D flip-flop
1991 Feb 08
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS1
MIN
TYP2
MAX
UNIT
VOH
High-level output voltage
VCC±10%, VIL = MAX, VIH = MIN, IOH = MAX
VCC – 2
V
VO
Low level output voltage
VCC = MIN, VIL = MAX,
IOL = 4mA
0.25
0.4
V
VOL
Low-level output voltage
CC
,
IL
,
VIH = MIN
IOL = 8mA
0.35
0.50
V
VIK
Input clamp voltage
VCC = MIN, II = IIK
–0.73
–1.5
V
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0V
100
µA
IIH
High-level input current
VCC = MAX, VI = 2.7V
20
µA
IIL
Low-level input current
VCC = MAX, VI = 0.5V
–0.1
mA
IO
Output current3
VCC = MAX, VO = 2.25V
–30
–112
mA
ICC
Supply current (total)
VCC = MAX
7
14
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
UNIT
MIN
MAX
fMAX
Maximum clock frequency
Waveform 1
60
MHz
tPLH
tPHL
Propagation delay
CP to Qn or CP to Qn
Waveform 1
3.0
5.0
13.0
16.0
ns
tPLH
Propagation delay, MR to Qn
Waveform 2
3.0
13.0
ns
tPHL
Propagation delay, MR to Qn
Waveform 2
8.0
18.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
UNIT
MIN
MAX
tsu(H)
tsu(L)
Setup time, High or Low
Dn to CP
Waveform 3
6.0
6.0
ns
th(H)
th(L)
Hold time, High or Low
Dn to CP
Waveform 3
0.0
0.0
ns
tw(H)
tw(L)
CP pulse width,
High or Low
Waveform 1
8.0
8.0
ns
tw(L)
MR pulse width, Low
Waveform 2
6.0
ns
tREC
Recovery time, MR to CP
Waveform 2
6.0
ns



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