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KSZ9563R データシート(PDF) 179 Page - Microchip Technology |
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KSZ9563R データシート(HTML) 179 Page - Microchip Technology |
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179 / 226 page  2017-2018 Microchip Technology Inc. DS00002419D-page 179 KSZ9563R 5.2.11.10 Port PTP Timestamp Interrupt Status Register Address: 0xNC14 - 0xNC15 Port N: 1-3 Size: 16 bits Bits Description Type Default 15 Port N Egress Timestamp for Sync Frame Interrupt Status (TS_SYNC_INT_STATUS) When this bit is set to 1, it indicates that the egress timestamp is available from Port N for the Sync frame. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Status bit in the Port Interrupt Status Register. R/W1C 0b 14 Port N Egress Timestamp for Pdelay_Req and Delay_Req Frames Interrupt Status (TS_PDLY_REQ_INT_STATUS) When this bit is set to 1, it indicates that the egress timestamp is available from Port N for the Pdelay_Req and Delay_Req frames. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Status bit in the Port Interrupt Status Register. R/W1C 0b 13 Port N Egress Timestamp for Pdelay_Resp Frame Interrupt Status (TS_PDLY_RESP_INT_STATUS) When this bit is set to 1, it indicates that the egress timestamp is available from Port N for the Pdelay_Resp frame. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Status bit in the Port Interrupt Status Register. R/W1C 0b 12:0 RESERVED RO 0x000 |
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