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KSZ9563R データシート(PDF) 180 Page - Microchip Technology |
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KSZ9563R データシート(HTML) 180 Page - Microchip Technology |
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180 / 226 page  KSZ9563R DS00002419D-page 180 2017-2018 Microchip Technology Inc. 5.2.11.11 Port PTP Timestamp Interrupt Enable Register 5.2.11.12 Port PTP Link Delay Register Address: 0xNC16 - 0xNC17 Port N: 1-3 Size: 16 bits Bits Description Type Default 15 Port N Egress Timestamp for Sync Frame Interrupt Enable (TS_SYNC_INT_ENB) When this bit is set to 1, the egress timestamp interrupt from Port N for the Sync frame is enabled. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Enable bit in the Port Interrupt Mask Register. R/W 0b 14 Port N Egress Timestamp for Pdelay_Req and Delay_Req Frames Interrupt Enable (TS_PDLY_REQ_INT_ENB) When this bit is set to 1, the egress timestamp interrupt from Port N for the Pdelay_Req and Delay_Req frames is enabled. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Enable bit in the Port Interrupt Mask Register. R/W 0b 13 Port N Egress Timestamp for Pdelay_Resp Frame Interrupt Enable (TS_PDLY_RESP_INT_ENB) When this bit is set to 1, the egress timestamp interrupt from Port N for the Pdelay_Resp frame is enabled. This bit is logical OR’ed together with the rest of the bits in this register and the output is shown as the PTP Interrupt Enable bit in the Port Interrupt Mask Register. R/W 0b 12:0 RESERVED RO 0x000 Address: 0xNC18 - 0xNC1B Port N: 1-3 Size: 32 bits Bits Description Type Default 31:0 PTP Port N Link Delay in nanoseconds This register is used to set the link delay value between port N and the link partner port. R/W 0x0000_0000 |
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