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TP-UART データシート(PDF) 3 Page - Siemens Semiconductor Group |
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TP-UART データシート(HTML) 3 Page - Siemens Semiconductor Group |
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3 / 26 page ![]() TP-UART-IC The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 3 1 The ANALOG - PART 1.1 General Device Specification 1.1.1 Absolute Maximum Ratings All voltages are referring to VB-. Currents are declared positive in case of flowing into pin. Symbol Parameter Min Max Unit Note VB+ positive line voltage -0.5 45 V 1) VCC positive voltage supply (internal or external supply) -0.5 7 V 2) VIF positive external voltage supply -0.5 7 V 2) VVSP interstate voltage (generated by on-chip regulator) -0.5 13 V 2) VTxO voltage on pin Tx0 -0.5 45 V 1) VRxIN voltage on pin RxIN -15 45 V 1) 4) VLV1 voltage on low voltage pins MODE0, MODE1, TSTIN, TESTMODE -0.5 VCC +0.5 V VLV2 voltage on low voltage pins TxD, RESn, TSTOUT, X1, X2, RxD -0.5 VIF +0.5 V ϑ j junction temperature 170 ο C ϑ S storage temperature -65 170 ο C VESD max. ESD stress voltage ± 1000 V 3) ILATCHUP static current for latchup initialization ± 50 mA Rth thermal resistance of the SOIC-20 package 58.5 71.5 K/W PV maximum power dissipation 1 W 1) During surge impulse is allowed and guaranteed by ext. elements: -20 V for 2 µsec and 65 V for 150 µsec 2) Allowed voltage relations: (a) VCC and VVSP normal / VB+ and VIF can be 0 V (b) VVSP normal / VCC , VB+ and VIF can be 0 V (c) VIF normal / VCC , VB+ and VVSP can be 0 V The combination: VCC normal and VVSP = 0 V is not allowed! 3) Human body model: 100 pF, 1.5 k Ω 4) Dynamic via CREC= 47 nF in case of switching-on the bus voltage 1.1.2 Recommended Operating Conditions Symbol Parameter Min Max Unit Note VB+ positive line voltage 20 33 V 1) VCC positive voltage supply for external supply (digital test modes with SHB = 0) 4.75 5.25 V VIF positive external supply voltage 3.0 5.25 V ϑ amb ambient temperature -25 85 ο C fclk clock frequency (external quartz) 4.9152 MHz 1) DC voltage of bus, with signal and compensation pulse 11 V ... 45 V 1.1.3 Humidity Level The valid susceptibility against humidity is described by JEDEC JESD22-A112, table 1, level 5. |
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