EM6635 datasheet(5/39 Pages) EMMICRO

5 / 39 page

EM6635

03/03 REV. B

 2002, EM Microelectronic-Marin SA

www.emmicroelectronic.com

Ram Architecture

Add

Page

64x4 direct addressable

RAM

Add

Page

64x4 indirect addressable

RAM

Add

Page

64x4 indirect addressable

RAM

Add

Page

64x4 indirect addressable

RAM

RAM_0

4 bit R/W

RAM_0

4 bit R/W

RAM_0

4 bit R/W

RAM_0

4 bit R/W

RAM_1

4 bit R/W

RAM_2

4 bit R/W

RAM_3

4 bit R/W

•

RAM_60

4 bit R/W

RAM_61

4 bit R/W

RAM_62

4 bit R/W

•

RAM_63

4 bit R/W

RAM_63

4 bit R/W

RAM_63

4 bit R/W

RAM_63

4 bit R/W

CPU Access Format:

Add Hex

Add Dec

bit3

bit2

bit1

bit0

RAM index

119

PageSel[1]

PageSel[0]

3. Operating Modes

The EM6635 has two low power operating modes, the active and the halt mode. The oscillator is always active in both

modes, whereas the RC-Oscillator is controlled by the CPU.

3.1 Active Mode:

The CPU is running. Instructions are read from the internal ROM and executed by the CPU.

After a system reset, the EM6635 is in active mode at ROM-address H000.

The active mode is stopped by executing the HALT instruction.

3.2 HALT Mode:

After a HALT instruction, the EM6635 is in HALT mode. The CPU is stopped. The 32kHz-oscillator, the prescaler are

running, whereas the timers, the watchdog timer, the BCD counters and the frequency generator are only working, if

activated before.

The RC-oscillator is stopped.

All registers, RAM and output buffers retain their states prior to HALT mode.

The HALT mode is left by an interrupt occurence or by a system reset.

The HALT command enables the global interrupt, i.e. DisINT=0.

Note: HALT mode is activated and XTAL Oscillator is not running. Only a system reset allows to go back in Active mode.

4. Power Supply

The EM6635 is supplied by a single external power supply between VDD (VBAT) and VSS (Ground).

A built-in voltage regulator generates VRR providing regulated voltage for the oscillator and the internal logic. The output

drivers are supplied directly from the external supply VDD. The internal power configuration is shown below in figure 3.

To supply the internal core logic it is possible to use either the internal voltage regulator (VRR < VDD) or VBAT directly (VRR =

VDD). The selection is done by mask option. By default the voltage regulator is used. Refer to chapter 17 for the mask

options.

The internal voltage regulator is chosen for high voltage systems. It saves power by reducing the internal core logic’s power

supply to an optimum value. However, due to the inherent voltage drop over the regulator the minimal VDD is restricted to

1.4V.

A direct VBAT connection can be selected for systems running on a 1.5V battery. The internal RFIL 1kOhm resistor

together with the external capacitor on VRR is filtering the VDD supply to the internal logic (as a low pass filter to protect the

logic against parasitic over- and under-voltages, e.g. created by piezo shocks).

In this case the minimum VDD can be as low as 1.2V.

The output buffers are directly supplied from the external power supply.

Note: State of I/O pads may not be defined until VRR reaches typ. 0.8V and Power-On-Reset supplied by VRR clears them

to inputs.

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