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MM54HC195J データシート(PDF) 1 Page - National Semiconductor (TI) |
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MM54HC195J データシート(HTML) 1 Page - National Semiconductor (TI) |
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1 / 6 page ![]() TLF5324 November 1995 MM54HC195MM74HC195 4-Bit Parallel Shift Register General Description The MM54HC195MM74HC195 is a high speed 4-bit SHIFT REGISTER utilizes advanced silicon-gate CMOS technolo- gy to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads at LS type speeds This shift register features parallel inputs parallel outputs J- K serial inputs SHIFTLOAD control input and a direct overriding CLEAR This shift register can operate in two modes PARALLEL LOAD SHIFT from QA towards QD Parallel loading is accomplished by applying the four bits of data and taking the SHIFTLOAD control input low The data is loaded into the associated flip flops and appears at the outputs after the positive transition of the clock input During parallel loading serial data flow is inhibited Serial shifting occurs synchronously when the SHIFTLOAD con- trol input is high Serial data for this mode is entered at the J-K inputs These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truth table The 54HC74HC logic family is functionally as well as pin- out compatible with the standard 54LS74LS logic family All inputs are protected from damage due to static dis- charge by internal diode clamps to VCC and ground Features Y Typical operating frequency 45 MHz Y Typical propagation delay 16 ns (clock to Q) Y Wide operating supply voltage range 2 – 6V Y Low input current 1 mA maximum Y Low quiescent current 80 mA maximum (74HC Series) Y Fanout of 10 LS-TTL loads Connection Diagram Dual-In-Line Package TLF5324 – 1 Top View Order Number MM54HC195 or MM74HC195 Function Table Inputs Outputs Clear Shift Clock Serial Parallel QA QB QC QD QD Load J K ABCD LX X X X X X X X L L L L H HL u XX a b c d a b c d d HH L X X X X X X QA0 QB0 QC0 QD0 QD0 HH u LH X X X X QA0 QA0 QBn QCn QCn HH u LL X X X X L QAn QBn QCn QCn HH u HH X X X X H QAn QBn QCn QCn HH u HL X X X X QAn QAn QBn QCn QCn H e high level (steady state) L e low level (steady state) X e irrelevant (any input including transitions) u e transition from low to high level a b c d e the level of steady-state input at inputs A B C or D respectively QA0 QB0 QC0 QD0 e the level of QA QB QC orQD respectively before the indicated steady-state input condi- tions were established QAn QBn QCn e the level of QA QB QC respectively before the most-recent transition of the clock C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A |
同様の部品番号 - MM54HC195J |
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同様の説明 - MM54HC195J |
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