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74HC393D データシート(PDF) 7 Page - NXP Semiconductors |
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74HC393D データシート(HTML) 7 Page - NXP Semiconductors |
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7 / 7 page  December 1990 7 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.7 Waveforms showing the clock (nCP) to output (1Qn,2Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the master reset (nMR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (nCP) removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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