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M95640-DF データシート(PDF) 20 Page - STMicroelectronics

部品番号 M95640-DF
部品情報  64-Kbit serial SPI bus EEPROM with high-speed clock
PDF  53 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95640-DF データシート(HTML) 20 Page - STMicroelectronics

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Instructions
M95640-W M95640-R M95640-DF
20/53
DocID16877 Rev 19
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5. Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit



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