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AS7C31026-15JC データシート(PDF) 4 Page - Alliance Semiconductor Corporation

部品番号 AS7C31026-15JC
部品情報  5V / 3.3V 64KX16 CMOS SRAM
PDF  10 Pages
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メーカー  ALSC [Alliance Semiconductor Corporation]
ホームページ  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C31026-15JC データシート(HTML) 4 Page - Alliance Semiconductor Corporation

  AS7C31026-15JC Datasheet HTML 1Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 2Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 3Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 4Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 5Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 6Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 7Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 8Page - Alliance Semiconductor Corporation AS7C31026-15JC Datasheet HTML 9Page - Alliance Semiconductor Corporation Next Button
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®
AS7C1026
AS7C31026
3/23/01; v.1.0
Alliance Semiconductor
P. 4 of 10
Read cycle (over the operating range)3,9
Shaded areas indicate preliminary information.
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
Parameter
Symbol
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
12
–
15
–
20
–
ns
Address access time
tAA
–12–15
–
20
ns
3
Chip enable (CE) access time
tACE
–12–15
–
20
ns
3
Output enable (OE) access time
tOE
–
6
–7
–8
ns
Output hold from address change
tOH
4–
4–
4–
ns
5
CE Low to output in low Z
tCLZ
0–
0–
0–
ns
4, 5
CE High to output in high Z
tCHZ
–
6
–6
–8
ns
4, 5
OE Low to output in low Z
tOLZ
0–
0–
0–
ns
4, 5
Byte select access time
tBA
–
6
–7
–8
ns
Byte select Low to low Z
tBLZ
0–
0–
0–
ns
4,5
Byte select High to high Z
tBHZ
–
6
–6
–8
ns
4,5
OE High to output in high Z
tOHZ
–
6
–6
–8
ns
4, 5
Power up time
tPU
0–
0–
0–
ns
4, 5
Power down time
tPD
–12–15
–
20
ns
4, 5
Undefined output/don’t care
Falling input
Rising input
tOH
tAA
tRC
tOH
DataOUT
Address
Data valid
Previous data valid
Data valid
tRC
tAA
tBLZ
tBA
tOE
tOLZ
tOH
tOHZ
tHZ
tBHZ
tACE
tLZ
Address
OE
CE
LB, UB
DataIN



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