9

AT49LL080

3273C–FLASH–5/03

WRITE: Write operations consist of START, CYCTYPE + DIR, ADDRESS, data, TAR

and SYNC fields as shown in Figure 2 and described in Table 6.

WRITE CYCLES: For write cycles, after the address is transferred, the master writes

the low nibble, then the high nibble of data. After that the master drives a TAR field to

give ownership of the bus to the LPC. After the second clock of the TAR phase, the tar-

get device assumes the bus and begins driving SYNC values. A TAR field to give control

back to the master follows this.

Figure 2. LPC Single-byte Write Waveforms

Note:

1. Field contents are valid on the rising edge of the present clock cycle.

MADDR

TAR

TAR

SYNC

CLK

LFRAME

LAD[3:0]

DATA

+ DIR

12

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

Table 6. LPC Write Cycle

Clock Cycle

Field Name

Field

Contents

(1)

LAD[3:0]

LAD[3:0]

Direction

Comments

1

START

0000b

IN

LFRAME must be active (low) for the part to respond. Only the

last start field (before LFRAME transitioning high) should be

recognized. The START field contents indicate an LPC memory

write cycle.

2

CYCTYPE

+ DIR

011xb

IN

Cycle Type: Indicates the type of cycle. Bits 3:2 must be 01 for a

memory cycle.

DIR: Bit 1 indicates the direction of the transfer (1 for write). Bit 0

is reserved.

3 - 10

ADDR

YYYY

IN

These eight clock cycles make up the 32-bit memory address.

YYYY is one nibble of the entire address. Addresses are

transferred most significant nibble first.

11

DATA

YYYY

IN

This field is the least significant nibble of the data byte. This data

is either the data to be programmed into the Flash memory or

any valid Flash command.

12

DATA

YYYY

IN

This field is the most significant nibble of the data byte.

13

TAR0

1111b

IN

then float

In this clock cycle, the master (ICH) has driven the bus to all 1s

and then floats the bus prior to the next clock cycle. This is the

first part of the bus “turnaround cycle”.

14

TAR1

1111b (float)

Float then

OUT

The LPC takes control of the bus during this cycle. During the

next clock cycle it will be driving the “sync” data.

15

RSYNC

0000b

OUT

The LPC outputs the values 0000, indicating that it has received

data or a Flash command.

16

TAR0

1111b

OUT

then Float

The LPC Flash memory drives LAD0 - LAD3 to 1111b to indicate

a turnaround cycle.

17

TAR1

1111b (float)

Float then

IN

The LPC Flash memory floats its outputs, the master (ICH) takes

control of LAD3 - LAD0.