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M25P20 データシート(PDF) 49 Page - STMicroelectronics

部品番号 M25P20
部品情報  2 Mbit, Low Voltage, Serial Flash Memory With 40MHz SPI Bus Interface
PDF  50 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M25P20 データシート(HTML) 49 Page - STMicroelectronics

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M25P20
Revision history
49/50
01-Dec-2005
7.0
50MHz operation added (see Table 20: AC Characteristics (50MHz
Operation, Device Grade 6)). All packages are ECOPACK®. Blank option
removed from under Plating Technology in Table 23: Ordering Information
Scheme. MLP package renamed as VFQFPN, silhouette and package
mechanical drawing updated (see package silhouette on page 1 and
Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat
Package No lead, 6x5mm, Package Outline. Note added to <Blue>Figure
26. and Figure 27 Read Identification (RDID) instruction added.
22-Dec-2005
8.0
tRES1 and tRES2 modified in Table 20: AC Characteristics (50MHz
Operation, Device Grade 6). Titles of Figure 27 and Table 22 corrected.
14-Apr-2006
9
The data contained in Table 11, Table 16 and Table 18 is no longer
preliminary data.
Figure 3: Bus Master and memory devices on the SPI Bus modified and
Note 2 added.
40MHz frequency condition modified for ICC3 in Table 14: DC
Characteristics (Device Grade 3).
Table 16: Instruction Times (Device Grade 3) shows preliminary data.
Device Grade distinction removed, Condition changed for the Data
Retention parameter in Table 11: Data Retention and Endurance.
VWI parameter for Device Grade 3 added to Table 8: Power-Up Timing
and VWI Threshold.
SO8 package specifications updated (see Figure 26 and Table 21).
/X Process added to Table 23: Ordering Information Scheme.
05-Jun-2006
10
tRES1 and tRES2 parameter timings changed for devices produced with the
“X” process technology in Table 18 and Table 19.
SO8 Narrow package specifications updated (see Figure 26 and
Table 21).
Table 24.
Document revision history (continued)
Date
Revision
Changes



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