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C5C5EDELTA-RM/D データシート(PDF) 85 Page - NXP Semiconductors

部品番号 C5C5EDELTA-RM/D
部品情報  C-5e NETWORK PROCESSOR SILICON REVISION A1
PDF  114 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

C5C5EDELTA-RM/D データシート(HTML) 85 Page - NXP Semiconductors

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AC Timing Specifications
85
03
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in
Table 44. The TBI interface timing is shown in Figure 16 and described in Table 45.
Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Tcmt
Tcmo
MII Tx
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tcgt
Tcgo
GMII / TBI Tx
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tctr
Tctd
Tcts
Tcth
TBI Rx
MII CPn_1 (TCLKI)
MII CPn_2-6 (Tx)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn+2_1 (RCLK)
Tcgr
Tcgs
Tcgh
GMII/MII Rx
CPn+2_2-6 (Rx)
CPn+3_1-6 (Rx)
CPn_0 (TCLK)
CPn_2-6 (Tx)
CPn+1_2-6 (Tx)
CPn+2_1 (RCLK)
CPn+3_1 (RCLKN)
CPn+2_2-6 (Rx)
CPn+3_2-6 (Rx)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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