データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

STM32U545NET6QTR データシート(PDF) 245 Page - STMicroelectronics

部品番号 STM32U545NET6QTR
部品情報  Ultra-low-power Arm® Cortex®-M33 MCUTrustZone®FPU,240 DMIPS, 512 KB flash memory, 274 KB SRAM, crypto
PDF  283 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U545NET6QTR データシート(HTML) 245 Page - STMicroelectronics

Back Button STM32U545NET6QTR Datasheet HTML 241Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 242Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 243Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 244Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 245Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 246Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 247Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 248Page - STMicroelectronics STM32U545NET6QTR Datasheet HTML 249Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 245 / 283 page
background image
DS14216 Rev 1
245/283
STM32U545xx
Electrical characteristics
258
5.3.30
PSSI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 33, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
PSSI_PDCK polarity: falling
•
PSSI_RDY and PSSI_DE polarity: low
•
Bus width: 16 lines
•
Data width: 32 bits
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Table 121. PSSI transmit characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
-
Frequency ratio DCMI_PDCK/fHCLK
--
0.4
-
PSSI_PDCK PSSI clock input
2.7 V ≤ VDD ≤ 3.6 V
-
64(2)
MHz
1.71 V ≤ VDD ≤ 3.6 V
-
47(2)
DPIXEL
PSSI clock input duty cycle
-
30
70
%
tOV(DATA)
Data output valid time
2.7 V ≤ VDD ≤ 3.6 V
-
14
ns
1.71 V ≤ VDD ≤ 3.6 V
-
21
tOH(DATA)
Data output hold time
1.71 V ≤ VDD ≤ 3.6 V
7-
tOV(DE)
DE output valid time
-
12.5
tOH(DE)
DE output hold time
6
-
tSU(RDY)
RDY input setup time
1.71 V ≤ VDD ≤ 3.6 V
0-
tH(RDY)
RDY input hold time
0
-
1. Evaluated by characterization. Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com